Santanu Mahapatra

Associate Professor
Department of Electronic Systems Engineering (formerly CEDT)
Indian Institute of Science (IISc)
Bangalore 560012

Research Area : Computational Nanoelectronics
Email : santanu@cedt.iisc.ernet.in
Phone : +91 80 23600810 Ext 116 / +91 80 22933090
Fax : +91 80 23600808




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Santanu Mahapatra received his B.E. (Bachelor of Engineering) degree from Jadavpur University, Kolkata, in the field of Electronics and Telecommunication in 1999, M. Tech (Master of Technology) degree in the field of Electrical Engineering (specializing in Microelectronics) in 2001 from Indian Institute of Technology (IIT) Kanpur, and Ph.D. degree from Swiss Federal Institute of Technology Lausanne (EPFL) in 2005. For his Ph.D. dissertation he worked on the modeling of Single Electron Transistor (SET) and its co-simulation and co-design with CMOS.

He joined Department of Electronic Systems Engineering (formerly CEDT), at Indian Institute of Science (IISc), Bangalore, India, as an assistant professor in August 2005 and then became Associate Professor in September 2010. He founded ‘Nano Scale Device Research Laboratory’ at Department of Electronic Systems Engineering (formerly CEDT) in 2006, where his research team works on compact modeling and simulation of emerging nanotechnologies and advanced CMOS devices. His research interests include device reliability, multi-gate transistors, tunnel field effect transistors, single electron transistors, and CMOS-nano hybridization. He has authored several research papers in international journals and refereed conferences. He is the author of the book ‘Hybrid CMOS Single Electron Transistor Device and Circuit Design’. He received IBM Faculty award in 2007, Microsoft Research India Outstanding Faculty Award in 2007 and the associateship of Indian Academy of Sciences in 2009. He is also the first time recipient of Ramanna Fellowship (2012 to 2015) in the discipline of electrical sciences from Department of Science and Technology, Government of India.

He is a senior member of IEEE (Electron Devices Society).

Courses offered :
E3225 - Art of Compact Modeling (August Term)
Syllabus: Band theory of solids, carrier transport mechanism, P-N junction diode, MOS Capacitor Theory, C-V characteristics, MOSFET operation, Types of compact models, Input Voltage Equation, Charge Linearization, Charge Modeling, Concept of Core Model, Quasi-static and Non-quasi-static Model, Introduction to Verilog-A, Brief overview of EKV and PSP

E3268 - Advanced CMOS and beyond CMOS (January Term)
Syllabus: ITRS, Problems with short channel devices: SCE, DIBL, leakage, Breakthrough Solutions: SOI, High K, metal gate, Non-classical MOSFET, CMOS scaling limit, Emerging nanotechnologies: SET, QCA, RSQF, RTD.

Sponsored Research Projects :

"Professional Compact Models for Next Generation Multiple-Gate MOS Transistors", funded by Department of Science and Technology (DST) under Ramanna Fellowship scheme (duration: 2012 to 2015).

Principal Investigator of the project "Ab initio analytical study of the effect of strain on silicon" funded by ISRO-IISC Space Technology Cell, (duration: 2010 to 2013)

Principal Investigator of the project "Compact modeling of asymmetric double gate nano scale transistors" funded by IFCPAR (Indo French Centre for the Promotion of Advanced Research) jointly with ISEP-Paris (duration: 2010 to 2013).

Co-Investigator of the project "Compact modeling of Carbon Nanotube transistors and their interconnects", funded by Department of Science and Technology (DST) under Fasttrack scheme, India (duration: 2009 to 2012).

Principal Investigator of the project, “Computationally Efficient Analytical Solution of Non-Linear Poisson’s Equations for Compact Modeling of Nano-Scale Multi-Gate Transistors”, funded by Department of Science and Technology (DST), India (duration: 2009 to 2012)

Principal Investigator of the project, "Single Electronics: Towards Hybrid CMOS-SET circuit design", funded by Council of Scientific and Industrial Research (CSIR), India (duration: 2007 to 2010)

Principal Investigator of the project, "Device reliability modeling and simulation for sub 65nm technology nodes", funded by IBM India Pvt Ltd. (duration: 2007 to 2010)

Principal Investigator of the project “Compact Modeling and Simulation of Silicon Nanowire “ funded by Department of Science and Technology (DST) under Fasttrack scheme, India (duration: 2006 to 2009)

Students and Associates:

Name
Program
Research Topic
Sitangshu Bhattacharya
Post Doctoral fellow and DST young scientist
 Carbon nanoelectronics
Jandhyala Srivatsava
Ph.D.(3rd year)
 Topics in Compact modeling
Ramakrishna Ghosh
Ph.D.(3rd year)
 Strained Silicon
Rekha Verma
Ph.D.(1st year)
 Carbon based interconnects
Neha Sharma
Ph.D.(1st year)
 Compact modeling
Abby Abraham
M.E. Micro (2nd year)
 Compact modeling
Sahithya Varma
Junior Research Fellow
 

Alumni

Name
Program (Year of Pass out)
Thesis Topic
Current Status
Pankaj Kumar Thakur
Ph.D.(2011)
 Topics in Compact Modeling  
A Rex
M.Sc. (2011)
 Thermal Conductivity Modeling for metallic Single Walled Carbon Nanotube Pursuing Ph.D. at IISc
Prabhat Ranjan
M.E. Micro (2010)
 Mixedmode Simulation of IDGMOS Tejas Network
Sudipta Sarkar
Best M.Tech Thesis Award under SMDP-II (2009-10)
M.E. Micro (2010)
 Non Quasi Static Modeling of Multi-Gate MOSFETs Pursuing Ph.D. at UT Dallas
Surya Shankar Dan
Tag Corporation Medal 2011
Ph.D. (2009)
 Impact of energy quantization on Single Electron Transistor devices and circuits Pursuing Post Doctoral at EPFL
Rakesh P
M.Sc. (2009)
 Analytical Modeling of Quantum Threshold Voltage for Short Channel Multi Gate Silicon Nanowire Transistors Pursuing PhD at university of Minnesota
Avinash Sahoo
Tag Corporation Medal 2010
M.Sc. (2009)
 On the modeling of inversion charge in Multi Gate FinFET  
Biswajit Ray
TechnoInventor Award 09 from India Semiconductor Association
M.Sc. (2008)
 Impact of Body Center Potential on the Electrostatics of Undoped Body Multi Gate Transistors: A Modeling Perspective Pursuing Ph.D. at Purdue
Ramesha A
M.Sc. (2008)
 Sub-threshold Slope Modeling & Gate Alignment Issues in Tunnel Field Effect Transistor DRDO
Sivakumar Bondada
(Jointly with Dr. S.Raha)
M.E. Micro (2008)
 Interconnect Modeling for Process Variability NVIDIA
Nayan Patel
TechnoInventor Award 08 from India Semiconductor Association
M.Sc. (2007)
 Performance Enhancement of the Tunnel Field Effect Transistor for Future Low Stand-by Power Applications Cypress Semiconductor
Chaitanya Sathe
M.E. Micro (2007)
 Modeling and Analysis of Noise Margin in SET Logic Pursuing Ph.D. at University of Illinois at Urbana Champagne
Shubhakar K.
(QIP Candidate)
M.E. Micro (2007)
 Simulation study of Carrier Transport in Silicon Nanowire Field Effect Transistor using Non-Equilibrium Green’s Function(NEGF) Approach Pursuing Ph.D. at National University of Singapore
Mastan Rao Kongara
(Jointly with TI)
M.E. Micro (2006)
 Testing for Parametric Faults in Analog Circuits Using Oscillation based Test Methodology BEL
Ratul Kumar Baruah
Research Assistant
   Faculty, Tezpur University, Assam

Publication List

Book

“Hybrid CMOS Single Electron Transistor Device and Circuit Design”, Santanu Mahapatra and Adrian M. Ionescu, Artech House Publication ISBN 1-59693-069-1, 2006.

Chapter in “Emerging Nanoelectronics: Life With and After CMOS” by Adrian M. Ionescu and Kaustav Banerjee, Editors, Kluwer Academic Publishers, ISBN: 1-4020-75332, 2004.

Journal Publications

  1. Srivatsava Jandhyala, Aby Abraham, Costin Anghel and Santanu Mahapatra, "Piecewise Linearization Technique for Compact Charge Modeling of Independent DG MOSFET", appearing in IEEE Transactions on Electron Devices 2012.

  2. Ramkrishna Ghosh, Sitangshu Bhattacharya and Santanu Mahapatra," Physics based band gap model for relaxed and strained [100] silicon nano wires", appearing in IEEE Transactions on Electron Devices 2012.

  3. Srivatsava Jandhyala, Rutwick Kashyap, Costin Anghel and Santanu Mahapatra, "A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry", IEEE Transactions on Electron Devices, Vol. 59, No. 4, pp. 1002-1007, 2012.

  4. Aby Abraham, Srivatsava Jandhyala and Santanu Mahapatra, "Improvements in Efficiency of Surface Potential Computation for Independent DG MOSFET", IEEE Transactions on Electron Devices, Vol. 59, No. 4, pp. 1199-1202, 2012.

  5. Sitangshu Bhattacharya and Santanu Mahapatra,"Quantum Capacitance in Bilayer Graphene Nanoribbon", appearing in Physica E 2012.

  6. Rekha Verma, Sitangshu Bhattacharya and Santanu Mahapatra, "Analytical Solution of Joule Heating Equation for Metallic Single Walled Carbon Nanotube Interconnects", IEEE Transactions on Electron Devices, Vol. 58, No. 11, pp. 3991-3996, 2011.

  7. Srivatsava Jandhyala and Santanu Mahapatra, "An efficient robust algorithm for the surface potential calculation of Independent DG MOSFET", IEEE Transactions on Electron Devices, Vol. 58, No. 6, pp. 1663-1671, 2011.

  8. Sitangshu Bhattacharya, Amalraj Rex and Santanu Mahapatra "Physics Based Thermal Conductivity Model for Metallic Single Walled Carbon Nanotube Interconnects", Vol. 32, No. 2, pp. 203, IEEE Electron Device Letters 2011.

  9. Pankaj Thakur and Santanu Mahapatra, "Large Signal Model For Independent DG MOSFET", IEEE Transactions on Electron Devices, Vol. 58, No. 1, pp. 46-52, 2011.

  10. Rakesh Kumar P and Santanu Mahapatra, “Analytical Modeling of Quantum Threshold Voltage for Triple Gate MOSFET”, Solid State Electronics, Vol. 54, 1586–1591 2010.

  11. Sudipta Sarkar, Ananda Shankar Roy and Santanu Mahapatra, "Unified Large and Small Signal Non Quasi-Static Model for Long Channel Symmetric DG MOSFET", Solid State Electronics, Vol. 54, pp. 1421-1429, 2010

  12. Sitangshu Bhattacharya and Santanu Mahapatra, “Negative Differential Conductance and Effective Electron Mass in Highly Asymmetric Ballistic Bilayer Graphene Nanoribbon” Physics Letters A, Vol. 374, pp. 2850–2855, 2010.

  13. Sitangshu Bhattacharya and Santanu Mahapatra, Simplified Theory of Carrier Back-Scattering in Semiconducting Carbon Nanotubes: a Kane's Model Approach, Journal of Applied Physics, Vol.107, Issue 9, pp. 094314, 2010. Also published in Virtual Journal of Nanoscale Science & Technology, Vol. 21, Issue 10, 2010

  14. Surya Shankar Dan and Santanu Mahapatra, "Impact of Energy Quantisation in SET Island on Hybrid CMOS-SET Integrated Circuits", IET Circuits Devices Systems, Vol. 4, Issue 5, pp. 449–457, 2010.

  15. Sivakumar Bondada, Soumyendu Raha and Santanu Mahapatra, An efficient reduction algorithm for computation of interconnect delay variability for statistical timing analysis in clock tree planning, appearing in Sadhana - Academy Proceedings in Engineering Science Vol. 35, Part 4, pp. 407–418, 2010.

  16. Sitangshu Bhattacharya and Santanu Mahapatra, "Analytical Study of Low Field Diffusive Transport in Highly Asymmetric Bilayer Graphene Nanoribbon", Vol. 10, No. 3, pp. 409-416, IEEE Transactions on Nanotechnology, 2010.

  17. Avinash Sahoo, Pankaj Kumar Thakur, and Santanu Mahapatra, "A Computationally Efficient Generalized Poisson Solution For Independent Double Gate Transistors", IEEE Transactions on Electron Devices, Vol. 57, no.3, pp. 632-636, 2010.

  18. Rakesh Kumar P and Santanu Mahapatra, "Quantum Threshold Voltage Modeling of Short Channel Quad Gate Silicon Nanowire Transistor", Vol. 10, No. 1, pp. 121-128, IEEE Transactions on Nanotechnology, 2010.

  19. Surya Shankar Dan and Santanu Mahapatra, "Impact of Energy Quantization Effects on the Performance of Current-Biased SET Circuits", IEEE Transactions on Electron Devices , Vol 56, No 8, pp.1562-1566, 2009.

  20. Surya Shankar Dan and Santanu Mahapatra, "Analysis of Energy Quantization Effects on Single Electron Transistor Circuits", in IEEE Transactions on Nanotechnology, Vol.9, No.1, pp. 38-45, 2010.

  21. Surya Shankar Dan and Santanu Mahapatra, "Modeling and Analysis of Energy Quantization Effects on Single Electron Inverter Performance", Physica E: Low-dimensional Systems and Nanostructures, Vol. 41, Issue 8, Pages 1410-1416, 2009.

  22. Sitangshu Bhattacharya and Santanu Mahapatra, "Influence of Band Non- Parabolicity on Few Ballistic Properties of III-V Quantum Wire Field Effect Transistors Under Strong Inversion", Journal of Computational and Theoretical Nanoscience, Vol.6, No.7, pp. 1605-1616, 2009.

  23. Biswajit Ray and Santanu Mahapatra, "Modeling of Channel Potential and Subthreshold Slop of Symmetric Double Gate Transistor", IEEE Transactions on Electron Devices, Vol. 56, No. 2, pp. 260-266, 2009.

  24. Ratul Kumar Baruah and Santanu Mahapatra, "Justifying threshold voltage definition for undoped body transistors through “crossover point” concept", Physica B: Condensed Matter, Volume 404, Issues 8-11, 1 May 2009, Pages 1029-1032.

  25. Sitangshu Bhattacharya, Surya Shankar Dan and Santanu Mahapatra, "Influence of band non-parabolicity on the quantized gate capacitance in delta-doped MODFED of III-V and related materials," Journal of Applied Physics, Vol. 104, No. 7, pp. 074304-1 to 074304-9, 2008.

  26. Biswajit Ray and Santanu Mahapatra, "Modeling and analysis of body potential of cylindrical Gate-All-Around nanowire transistor", IEEE Transactions on Electron Devices, Vol. 55, No. 9, pp. 2409-2416, 2008.

  27. Nayan B Patel, Ramesha A and Santanu Mahapatra, "Drive Current Boosting of n-type Tunnel FET with Strained SiGe layer at Source", Microelectronics Journal Vol 39, Issue 12, PP. 1671-1677, 2008.

  28. Chaitanya Sathe, Surya Shankar Dan, and Santanu Mahapatra, "Assessment of SET logic Robustness through Noise Margin Modeling", IEEE Transactions on Electron Devices, Vol. 55, No. 3, pp. 909-915, 2008.

  29. Serge Ecoffey, Didier Bouvet, Santanu Mahapatra, Gilles Reimbold, and Adrian Mihai Ionescu, "Electrical Conduction in 10nm-thin Polysilicon Wires from 4K to 400K and their Operation for Hybrid Memory", Japanese Journal of Applied Physics Part 1, Vol. 45, No. 6, June 2006.

  30. Santanu Mahapatra and Adrian Mihai Ionescu, “Realization of multiple value logic and memory by hybrid SETMOS architecture”, IEEE Transactions in Nanotechnology, Vol. 4, No. 6, pp. 705 - 714, 2005.

  31. Serge Ecoffey, Vincent Pott, Santanu Mahapatra, Didier Bouvet, Pierre Fazan, Adrian Mihai Ionescu, “A Hybrid CMOS-SET co-fabrication Platform Using Nanograin Polysilicon Wires”, Microelectronic Engineering, Vol 78-79, pp.239-243, 2005.

  32. Santanu Mahapatra, Vaivabh Vaish, Christoph Wasshuber, Kaustav Banerjee and Adrian Mihai Ionescu, “Analytical Modelling of Single Electron Transistor (SET) for Hybrid CMOS-SET Analog IC Design”, IEEE Transactions on Electron Device, Vol. 51, No. 11,pp. 1772-1782, 2004.

  33. Santanu Mahapatra and Adrian Mihai Ionescu, “A Novel Elementary Single Electron Transistor Negative Differential Resistance Device”, Japanese Journal of Applied Physics, Part 1, Vol. 43, No. 2, pp. 538-539, 2004.

  34. Adrian Mihai Ionescu, Santanu Mahapatra, and Vincent Pott, “Hybrid SETMOS Architecture with Coulomb Blockade Oscillations and High Current Drive”, IEEE Electron Device Letters, Vol.25, No.6, pp. 411-413, 2004.

  35. Santanu Mahapatra, Adrian Mihai Ionescu, and Kaustav Banerjee, “A Quasi-Analytical SET Model for Few Electron Circuit Simulation”, IEEE Electron Device Letters, Vol.23, No.6, pp. 366-368, June 2002.

  36. Santanu Mahapatra, Adrian Mihai Ionescu, Kaustav Banerjee and Michel Declercq, “A SET Based Quantizer Circuit for Digital Communications”, IEE Electronics Letters, Vol. 38, No. 10, pp. 443-445, May 2002.

Patent

  1. Santanu Mahapatra and Nayan Patel, "An n-type tunnel FET device with strained SiGe layer at source", Applied for Indian patent, Application Number: 02057/CHE/2007, September 2007.

Conference Publications

  1. Sudipta Sarkar, Ananda Shankar Roy and Santanu Mahapatra, "A Non Quasi-Static Small Signal Model for Long Channel Symmetric DG MOSFET", appearing in International Conference on VLSI Design 2010 , India.

  2. Sitangshu Bhattacharya and Santanu Mahapatra, "Does Nanotubes and Nanowires Exhibit Negative Capacitances?", appearing in International Workshop on Physics for Semiconductor Devices (IWPSD) 2009 , India.

  3. Surya Shankar Dan and Santanu Mahapatra, "Impact of Energy Quantization in SET island on Hybrid CMOS-SET Integrated Circuits", appearing in International Workshop on Physics for Semiconductor Devices (IWPSD) 2009 , India.

  4. Surya Sankar Dan and Santanu Mahapatra, "Analysis of the energy quantization effects on SET inverter performance using noise margin modeling and monte carlo simulation", International Conference on VLSI Design 2009, India.

  5. Ratul Baruah and Santanu Mahapatra, “Concept of ‘crossover point’ and its application on threshold voltage definition for undoped-body transistors”, International Conference On VLSI Design 2009, India.

  6. Santanu Mahapatra, Ramesha A and Nayan Patel, “Tunnel FET: Nano-Scale Switch For Low Standby Power Applications”, International Conference on Nano and Microelectronics (ICONAME) 2008, Puducherry, India

  7. Biswajit Ray and Santanu Mahapatra, "A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor", International Conference on VLSI Design 2008, Hyderabad, India

  8. Biswajit Ray and Santanu Mahapatra, "Analytical Potential Model for Omega Gate Cylindrical Nanowire Transistor", International Conference on Nano and Microelectronics 2008, Puducherry, India

  9. Nayan B Patel and Santanu Mahapatra, “Performance Enhancement of the Tunnel Field Effect Transistor using SiGe Source, International Workshop on Physics for Semi-conductor Devices 2007, Mumbai, India

  10. Biswajit Ray, Shubhakar, and Santanu Mahapatra, “Necessity for quatum simulation for future technology nodes, International Workshop on Physics for Semi-conductor Devices 2007, Mumbai, India

  11. Shubhakar, Biswajit Ray and Santanu Mahapatra, "Challenges Posed to the State of the Art Device Simulators in Nanoscale Regime", VLSI Design And Test Symposium 2007, Kolkata, India

  12. Shubhakar and Santanu Mahapatra, "Effects of material properties and device parameters on the performance of Silicon nanowire FET", ANM-2007, International conference, IIT Bombay, India

  13. Ashish Pal, Saptarshi Das, Biswajit Ray and Santanu Mahapatra, "A New Spice Simulator for Single Electron Transistor Based Integrated Circuits", VLSI Design And Test Symposium 2007, Kolkata, India

  14. Nayan B. Patel and Santanu Mahapatra, "A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance for Low Stand-By Power Applications", VLSI Design And Test Symposium 2007, Kolkata, India

  15. Chaitanya Sathe and Santanu Mahapatra, "Modeling and Analysis of Noise Margin in SET Logic", International Conference on VLSI Design 2007, Bangalore, India

  16. Nayan B. Patel and Santanu Mahapatra, "Tunnel FET - A Novel Device with Sub-Threshold Swing less than 60 mV/decade for Future Low Stand-by Power Applications", National Conference on VLSI and Communication Engineering 2007, Kottayam, India

  17. Serge Ecoffey, Vincent Pott, Didier Bouvet, Marco Mazza,Santanu Mahapatra, Alexandre Schmid, Yusuf Leblebici, Michel J. Declercq, Adrian M. Ionescu, “Nano-Wires for Room Temperature Operated Hybrid CMOS-NANO Integrated Circuits”, International Solid State Circuits Conference (ISSCC), Vol. 1, pp. 260-263, 2005.

  18. Adrian Mihai Ionescu, Vincent Pott, Serge Ecoffey, Santanu Mahapatra, Kirsten Moselund, Paolo Dainesi, Kathy Buchheit, Marco Mazza, “Emerging nanoelectronics: multi-functional nanowire”, Proc. of CAS 2004, vol. 1, pp. 3-8, October, Romania.

  19. Serge Ecoffey, Vincent Pott, Santanu Mahapatra, Didier Bouvet, Pierre Fazan, Adrian Mihai Ionescu, “A Hybrid CMOS-SET co-fabrication Platform Using Nanograin Polysilicon Wires”, Micro and Engineering (MNE) 2004, September, Rotterdam, Nederland.

  20. Santanu Mahapatra and Adrian Mihai Ionescu, "A novel single electron SRAM architecture", Proc. of IEEE NANO 2004, August, Munich, Germany.

  21. Santanu Mahapatra, Vincent Pott, Serge Ecoffey, Alexandre Schmid, Christoph Wasshuber, Kaustav Banerjee, Yusuf Leblebici, Michel Declercq, Joseph Tringe, Adrian Mihai Ionescu, “SETMOS: A Novel True Hybrid SET-CMOS High Current Coulomb Blockade Oscillation Cell for Future Nano-Scale Analog ICs”, IEEE International Electron Device Meeting (IEDM) 2003, December, pp. 703-706, Washington DC, USA.

  22. Santanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian Mihai Ionescu, “A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits”, International Conference on Computer Aided Design (ICCAD) 2003, pp. 497-502, November, San Jose, USA.

  23. Santanu Mahapatra, Vincent Pott, and Adrian Mihai Ionescu, “Few Electron Negative Differential Resistance (NDR) Devices”, International Semiconductor Conference (CAS) 2003, Vol.1, pp. 51-54, September, Sinaia, Romania.

  24. Santanu Mahapatra, Vincent Pott, Adrian Mihai Ionescu, “SETMOS-A High Current Coulomb Blockade Oscillation Device”, European Solid-State Device Research Conference (ESSDERC) 2003, pp. 183-186, September, Estoril, Portugal.

  25. Santanu Mahapatra, Adrian Ionescu, Kaustav Banerjee and Michel Declercq, “Modelling and analysis of power dissipation in Single Electron logic”, IEEE International Electron Device Meeting (IEDM) 2002, pp. 323-326, December, San Francisco, USA.

  26. Santanu Mahapatra, Adrian Ionescu and Kaustav Banerjee, “Quasi-analytical modelling of drain current and conductances of single electron transistors with mib”, 32nd European Solid-State Device Research Conference (ESSDERC) 2002, pp. 391-394, September, Florence, Italy.

  27. Adrian Ionescu, Michel Declercq, Santanu Mahapatra, Kaustav Banerjee, and Jacques Gautier, “Few Electron Devices: Towards Hybrid CMOS-SET Integrated Circuits”, 39th Design Automation Conference (DAC) 2002, pp. 88-93, June, New Orleans, Louisiana, USA.

  28. Adrian Ionescu, Michel Declercq, Santanu Mahapatra and Kaustav Banerjee, “Teaching microelectronics in the silicon ICs showstopper zone: a course on ‘Ultimate devices and circuits: towards quantum electronics’”, 4th European workshop on Microelectronics Education (EWME) 2002, May, Spain.

  29. Santanu Mahapatra, Adrian Ionescu, Kaustav Banerjee and Michel Declercq, “A SET Quantizer Circuit aiming at Digital Communication System”, IEEE International Symposium on Circuits and Systems (ISCAS) 2002, pp. V860-V863, May, Scottsdale, Arizona.